Fabricating fin structures with doped middle portions

ABSTRACT

Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Non-Provisional patentapplication Ser. No. 14/725,552, filed May 29, 2015, which claimsbenefit of U.S. Provisional Patent Application No. 62/101,657, filedJan. 9, 2015, which are hereby incorporated herein by reference in theirentirety.

FIELD OF THE INVENTION

The present invention relates to methods of fabricating semiconductorstructures and more particularly to methods of fabricating finstructures with doped middle portions.

BACKGROUND OF THE INVENTION

Complementary metal oxide semiconductor (CMOS) technology continues tobe widely used in the fabrication of integrated circuits. As integratedcircuit density continues to increase, semiconductor devices withthree-dimensional vertical fin structures have been developed to replaceconventional planar devices, because devices with fin structures canprovide higher performance at a smaller footprint than planar devices.However, increased density, with smaller critical dimensions, canintroduce fabrication challenges. Therefore, further enhancements infabrication techniques for fin structures continue to be pursued.

BRIEF SUMMARY

The shortcomings of the prior art are overcome, and additionaladvantages are provided, through the provision, in one aspect, of amethod. The method includes: fabricating at least one fin structure, theat least one fin structure having a doped middle portion separating anupper portion from a lower portion, and the fabricating comprising:providing an isolation layer in contact with the lower portion of the atleast one fin structure; forming a doping layer above the isolationlayer and in contact with the at least one fin structure; and annealingthe doping layer to diffuse dopants therefrom into the at least one finstructure to form the doped middle portion thereof, wherein theisolation layer inhibits diffusion of dopants from the doping layer intothe lower portion of the at least one fin structure.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more aspects of the present invention are particularly pointedout and distinctly claimed as examples in the claims at the conclusionof the specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 depicts embodiments of processes for fabricating at least one finstructure, in accordance with one or more aspects of the presentinvention;

FIG. 2A is a cross sectional elevational view of a structure found in asemiconductor fabrication process, in accordance with one or moreaspects of the present invention;

FIG. 2B depicts the structure of FIG. 2A after forming a finstructure(s) extending above a substrate thereof, in accordance with oneor more aspects of the present invention;

FIG. 2C depicts the structure of FIG. 2B after providing an isolationlayer in contact with the fin structure(s) thereof, in accordance withone or more aspects of the present invention;

FIG. 2D depicts the structure of FIG. 2C after removing some of theisolation layer to reveal portion(s) of the fin structure(s) thereof, inaccordance with one or more aspects of the present invention;

FIG. 2E depicts the structure of FIG. 2D after forming a doping layerabove the isolation layer and in contact with the fin structure(s)thereof, in accordance with one or more aspects of the presentinvention;

FIG. 2F depicts the structure of FIG. 2E after providing anotherisolation layer above the doping layer thereof, in accordance with oneor more aspects of the present invention;

FIG. 2G depicts the structure of FIG. 2F after recessing the dopinglayer to reveal an upper portion(s) of the fin structure(s) thereof, inaccordance with one or more aspects of the present invention;

FIG. 2H depicts the structure of FIG. 2G after annealing the dopinglayer to diffuse dopants thereof into the fin structure(s) to form dopedmiddle portion(s) thereof, in accordance with one or more aspects of thepresent invention; and

FIG. 2I is a plan view of the structure of FIG. 2H, in accordance withone or more aspects of the present invention.

DETAILED DESCRIPTION

Aspects of the present invention and certain features, advantages, anddetails thereof, are explained more fully below with reference to thenon-limiting examples illustrated in the accompanying drawings.Descriptions of well-known materials, fabrication tools, processingtechniques, etc., are omitted so as not to unnecessarily obscure theinvention in detail. It should be understood, however, that the detaileddescription and the specific examples, while indicating aspects of theinvention, are given by way of illustration only, and not by way oflimitation. Various substitutions, modifications, additions, and/orarrangements, within the spirit and/or scope of the underlying inventiveconcepts will be apparent to those skilled in the art from thisdisclosure.

The present disclosure describes, in part, fabrication methods for finstructures with doped middle portions. By way of explanation, in thefabrication of integrated circuits with smaller critical dimensions andgreater device density, semiconductor devices with three-dimensionalvertical fin structures are desirable to allow higher performance, suchas a higher ratio of on-current to off-current.

For instance, in one fabrication example, channel regions oftransistors, such as fin-type field-effect transistors (fin FETs), areformed within upper portions of the fin structures. Next, conformal gatestructures are formed to wrap around the upper portions of the finstructures, to provide gate control on three sides of the upper portionof the fin structure, allowing for an applied gate voltage to bettercontrol turning the transistor on or off. Because the conformal gatestructures can be in contact with three sides of the fin structures, theentire upper portions of the fin structures can be active regions of thetransistors, facilitating increased on-current.

However, when such transistors are fabricated at small criticaldimensions, such as gate lengths of 20 nanometers or less, there can beproblems, including short channel effects, such as leakage currentswhich flow from the channel regions to the underlying substrate evenwhen the transistors are turned off by controlling the gate voltage. Forexample, leakage current increases power consumption, generates heat,and otherwise decreases performance of the transistor. In order toreduce and/or eliminate such leakage currents, the present techniqueprovides for forming a doped middle portion of the fin structure,located below the upper portion. In one example, the doped middleportion can include relatively high channel doping, with the doping typebeing opposite to the doping type of the source region and/or drainregion doping, and can be used to reduce leakage currents, such aspunch-through leakage current, and the doped middle portions can bereferred to as punch-through stop portions. In such an example, leakagecurrents will be inhibited from flowing between upper portions and lowerportions by doped middle portions of fin structures.

In addition, doping the middle portions of fin structures can bedifficult to achieve without introducing other problems or complexities.For example, dopants can be implanted from the top of the fin structuresusing a specific implantation energy selected so that the dopants reacha specific depth into the fin structures, for example, a target depthbeing the middle portions of the fin structures. However, because theimplanted dopants will have a range of energies, for example, followinga Gaussian distribution, in such a case, some concentration of dopantswill appear even in the upper portions of the fin structures, as well asthe lower portions of the fin structure. Therefore, dopants in the upperportions of the fin structure can have adverse effects. For instance,such dopants can modify the threshold voltage characteristics oftransistors formed with channel regions including the upper portions ofthe fin structure. In addition, dopants in upper portions of finstructures can introduce mobility degradation for fin-type devices whichuse the upper portions of the fin structures as channel regions.

In certain applications, such as static random access memory (SRAM),multiple transistors are used to form a memory cell, and the thresholdvoltages must match closely. For example, random dopant concentrationsin the upper portions of the fin structure can lead to device faults andpoor performance. In addition, dopants in the lower portions of the finstructure can be problematic for transistors formed in a substrate well,because the dopants can interfere with the substrate dopants andinterrupt the junction, leading to well leakage.

In another example, various applications can require transistors withdifferent threshold voltage characteristics. Therefore, in the design ofintegrated circuits, it may be desirable to optimize leakage powerconsumption and speed of the integrated circuit by having differentportions of the integrated circuit use transistors with differentthreshold voltage characteristics. For example, it may be desirable toperform arithmetic or logic functions at a relatively high speed toenable advanced features, but perform memory storage at a lower speed tosave power. In addition, because CMOS technology makes use of n-type andp-type transistors, there can be a requirement for matched thresholdvoltages of n-type and p-type transistors.

Advantageously, the present techniques allow for the enhancedfabrication of fin structures with doped middle portions. For instance,the present techniques provide self aligned formation of doped middleportions of fin structures to reduce and/or eliminate leakage currentsbetween source and drain regions (e.g., through lower portions of thefin structures which are not surrounded and/or controlled by a gatestructure). In addition, the present techniques allow for formation ofdoped middle portions without introducing dopants into upper or lowerportions of the fin structures to prevent threshold voltage mismatchand/or well leakage due to interruption of the well junctions. Further,the present techniques allow for the provision of multiple thresholdvoltages.

Reference is made below to the drawings, which are not drawn to scalefor ease of understanding, wherein the same reference numbers usedthroughout different figures designate the same or similar components.

FIG. 1 depicts embodiments of processes for fabricating at least one finstructure, in accordance with one or more aspects of the presentinvention.

In one embodiment, a method includes fabricating at least one finstructure, the at least one fin structure comprising a doped middleportion separating an upper portion from a lower portion 100, and thefabricating 100 includes: providing an isolation layer in contact withthe lower portion of the at least one fin structure 110; forming adoping layer above the isolation layer and in contact with the at leastone fin structure 120; and annealing the doping layer to diffuse dopantstherefrom into the at least one fin structure to form the doped middleportion thereof, wherein the isolation layer inhibits diffusion ofdopants from the doping layer into the lower portion of the at least onefin structure 130.

In another embodiment, the method includes: fabricating a transistorhaving a channel region, the channel region comprising the upper portionof the at least one fin structure, where the doped middle portion of theat least one fin structure reduces leakage current between the sourceregion and the drain region of the transistor (e.g., through a lowerportion of the at least one fin structure).

In a further embodiment, the at least one fin structure comprises atleast one first fin structure and at least one second fin structure, andthe fabricating 100 comprises: forming the doping layer with a firstthickness in contact with the at least one first fin structure and asecond thickness in contact with the at least one second fin structure;and annealing the doping layer to form a first doped middle portion ofthe at least one first fin structure with the first thickness and asecond doped middle portion of the at least one second fin structurewith the second thickness, wherein the first thickness and the secondthickness are different thicknesses.

In one implementation, the method comprises: fabricating an integratedcircuit comprising a first transistor and a second transistor, the firsttransistor comprising the at least one first fin structure and thesecond transistor comprising the at least one second fin structure, andthe first thickness of the first doped middle portion facilitates thefirst transistor having a first threshold voltage characteristic and thesecond thickness of the second doped middle portion facilitates thesecond transistor having a second threshold voltage characteristic,wherein the first threshold voltage characteristic and the secondthreshold voltage characteristic are different threshold voltagecharacteristics.

In another implementation, the at least one fin structure comprises atleast one first fin structure and at least one second fin structure, andthe fabricating 100 comprises: forming the doping layer with firstdopants in contact with the at least one first fin structure and seconddopants in contact with the at least one second fin structure, whereinthe first dopants and second dopants are different dopants; andannealing the doping layer to form a first doped middle portion of theat least one first fin structure having the first dopants and a seconddoped middle portion of the at least one second fin structure having thesecond dopants. In such a case, the first dopants can comprise n-typedopants and the second dopants can comprise p-type dopants, and themethod can comprise: fabricating an integrated circuit comprising ap-type transistor and an n-type transistor, the p-type transistorcomprising the at least one first fin structure and the n-typetransistor comprising the at least one second fin structure.

In a further implementation, the at least one fin structure comprises atleast one first fin structure and at least one second fin structure, andthe fabricating 100 comprises: forming the doping layer with a firstinitial dopant concentration in contact with the at least one first finstructure and a second initial dopant concentration in contact with theat least one second fin structure, wherein the first initial dopantconcentration and the second initial dopant concentration are differentconcentrations; and annealing the doping layer to form a first middleportion of the at least one first fin structure with a first finaldopant concentration and a second middle portion of the at least onesecond fin structure with a second final dopant concentration, whereinthe first final dopant concentration and the second final dopantconcentration are different dopant concentrations. In such a case, forexample, the method comprises: fabricating an integrated circuitcomprising a first transistor and a second transistor, the firsttransistor comprising the at least one first fin structure and thesecond transistor comprising the at least one second fin structure, andthe first concentration of the dopants facilitates the first transistorhaving a first threshold voltage characteristic and the secondconcentration of the dopants facilitates the second transistor having asecond threshold voltage characteristic, wherein the first thresholdvoltage characteristic and the second threshold voltage characteristicare different threshold voltage characteristics.

In one example, the fabricating 100 comprises: providing a substrateunderlying the at least one fin structure; implanting other dopants intothe substrate to form a substrate well region thereof, wherein the otherdopants and the dopants of the doping layer are different dopants.

In another example, the fabricating 100 comprises fabricating the dopedmiddle portion of the at least one fin structure without doping theupper portion or the lower portion of the at least one fin structurenotwithstanding the diffusing of the dopants during the annealing.

In a further example, the method further includes: forming a conformalgate structure over the isolation material and in contact with the atleast one fin structure, wherein the isolation material facilitatesaligning the conformal gate structure in contact with the upper portionof the at least one fin structure but not in contact with the dopedmiddle portion thereof.

In one embodiment, providing the isolation layer 110 comprises providingthe isolation layer with a thickness, the thickness of the isolationlayer setting the lower portion of the at least one fin structure withthe thickness. In another embodiment, forming a doping layer 120comprises forming the doping layer with a thickness, the thickness ofthe doping layer setting the doped middle portion of the at least onefin structure with the thickness. In a further embodiment, the annealing120 comprises oxidizing the doping layer and the at least one finstructure.

In one implementation, forming the doping layer 120 comprisesepitaxially forming a material over the at least one fin structure toform the doping layer. In such a case, in one example, the materialcomprises at least one of silicon or germanium. In anotherimplementation, forming the doping layer 120 comprises providing amaterial, and concurrently therewith doping the material with thedopants, to form the doping layer. In a further implementation, thedopants comprise at least one of boron, phosphorous or arsenic.

In one example, forming the doping layer 120 comprises providing aborophosphosilicate glass to form the doping layer. In another example,a concentration of the dopants in the middle portion of the at least onefin structure is between 10¹⁸ to 10²⁰ atoms per cm³.

FIG. 2A is a cross sectional elevational view of a structure 200 foundin a semiconductor fabrication process, in accordance with one or moreaspects of the present invention. In the embodiment of FIG. 2A,structure 200 includes a substrate 205, and can have multiple regionssuch as first region 201 and second region 202.

By way of explanation, in one embodiment, substrate 205 can be asemiconductor wafer, such as a silicon wafer. For instance, in asemiconductor fabrication process, numerous integrated circuits, orchips, can be formed in multiple die regions of the semiconductor wafer.In addition, the semiconductor wafer can be subsequently diced intoindividual integrated circuits, or chips, and packaged for use inelectronics devices or components. Further, during such a fabricationprocess, the techniques described herein can be used to form numerousdifferent structures in numerous different regions of the substrate.

In one embodiment, substrate 205 can be a bulk semiconductor materialsuch as a bulk silicon wafer. In another embodiment, substrate 205 caninclude silicon (Si), single crystal Si, polycrystalline Si, amorphousSi, Si-on-nothing (SON), Si-on-insulator (SOI), or Si-on-replacementinsulator (SRI). In a further embodiment, substrate 205 can be n-type orp-type doped. In one particular example, substrate 205 can have athickness of approximately 600-900 micrometers.

FIG. 2B depicts structure 200 after forming fin structure(s) 210extending above substrate 205, in accordance with one or more aspects ofthe present invention. In one embodiment, fin structure(s) 210 can beformed by removal of one or more portions of substrate 205, resulting infin structure(s) formed of the same material as substrate 205, which maybe, for example a semiconductor or crystalline material.

For instance, substrate 205 may be patterned with fin structure(s) 210using one or more techniques, such as: direct lithography; sidewallimage transfer technique; extreme ultraviolet lithography (EUV); e-beamtechnique; litho-etch litho-etch; or litho-etch litho-freeze. In such acase, following patterning, removal of material of substrate 205 can beachieved using any suitable etching process, for example, anisotropicdry etching or reactive-ion-etching (ME) in sulfur hexafluoride (SF₆).Although the following numbers are relative and the heights could vary,in one specific example, fin structure(s) 210 can have a height of about40 to 300 nanometers and a length of about one micrometer, severalmicrometers, or the diameter of the entire wafer, and the width of thefin structures can be approximately 1 to 20 nanometers.

In one embodiment, numerous fin structures may be formed over an entirewafer or an entire die of a wafer. In such an embodiment, the finstructures may be formed at the smallest critical dimension during asingle initial fin structure formation process, and some portions of thefin structures can removed during subsequent fabrication steps.

FIG. 2C depicts structure 200 after providing an isolation layer 220 incontact with the fin structure(s) 210 thereof, in accordance with one ormore aspects of the present invention. In one embodiment, isolationlayer 220 includes an insulator, for example an oxide such as silicondioxide or tetraethyl orthosilicate. In another embodiment, isolationlayer 220 can be provided using chemical vapor deposition or a highaspect ratio process. For example, isolation layer 220 can be providedin order to electrically isolate fin structures from one another.

FIG. 2D depicts structure 200 after removing some of isolation layer 220to reveal portion(s) of the fin structure(s) 210 thereof, in accordancewith one or more aspects of the present invention. In one embodiment, afin reveal process can employ any suitable etching process, for example,an isotropic dry etching process, to remove some of isolation layer 220to reveal fin structure(s) 210. In one specific example, a dry etchingprocess, such as a SiCoNi etching may be employed.

FIG. 2E depicts structure 200 after forming a doping layer 230 aboveisolation layer 220 and in contact with fin structure(s) 210 thereof, inaccordance with one or more aspects of the present invention. Dopinglayer 230 can be or include a variety of different materials thatinclude n-type and/or p-type dopants in varying concentrations. N-typeand p-type dopants are impurities that are added to modify electricalproperties of semiconductors. For instance, n-type dopants includephosphorous, arsenic, and antimony, or any combination thereof, andp-type dopants include boron, gallium, and aluminum, or any combinationthereof. In addition, doping layer 230 can have a concentration ofapproximately 10¹⁵ to 10²³ atoms per cm³.

In one embodiment, doping layer 230 is or includes a borophosphosilicateglass (BPSG), a phosphorous silicate glass (PSG), a boron silicate glass(BSG), or any combination thereof. In another embodiment, doping layer230 is or includes an oxide, such as silicon dioxide. In a furtherembodiment, doping layer 230 is or includes a semiconductor material,such as silicon or silicon germanium.

In one example, doping layer 230 can be formed using chemical vapordeposition (CVD), atomic layer deposition (ALD), or spin coating. Inanother example, doping layer 230 can be formed by an epitaxialformation process (for example, if doping layer 230 includes acrystalline material).

For example, dopants may be introduced into doping layer 230 duringformation above isolation layer 220 (for example, in situ doping). Inaddition, dopants may be introduced into the doping layer after thedoping layer has been formed above the isolation layer, using, forexample, ion implantation. In one specific example, dopants may beintroduced with ion implantation with an energy of approximately 5-30kilo electron volts (keV).

In one embodiment, doping layer 230 can be provided with differentthicknesses in different regions of structure 200 through the use of aseries of mask steps that selectively expose some regions and notothers, followed by provision of material to form doping layer 230 withthe appropriate thickness in the exposed regions. In another embodiment,material can be added (or removed) so that different regions havedifferent thicknesses of the doping layer.

In a further embodiment, doping layer 230 can have different dopants indifferent regions and/or have different concentrations of dopants indifferent regions. For instance, one region can have n-type dopants, andanother region can have p-type dopants, thereby facilitating formationof CMOS integrated circuits. In addition, different concentrations ofthe same and/or different dopants can be used to achieve multipledifferent threshold voltage characteristics for transistors formed indifferent regions (e.g., transistors having channel regions includingthe fin structures), because different doping concentrations can be usedto tune threshold voltage characteristics because the dopants under achannel region of a transistor can change the electrical properties ofthe operational transistors.

FIG. 2F depicts structure 200 after providing another isolation layer240 above doping layer 230 thereof, in accordance with one or moreaspects of the present invention. In one embodiment, isolation layer 240can include any of the materials described above with respect toisolation layer 220, and isolation layer 240 can include the samematerials or different materials as isolation layer 220. using adeposition process to provide an isolation layer fill material;

FIG. 2G depicts structure 200 after recessing doping layer 230 to revealupper portion(s) 211 of fin structure(s) 210 thereof, in accordance withone or more aspects of the present invention.

In the embodiment of FIG. 2G, doping layer 230 has been recessed to thelevel of isolation layer 240. For instance, isolation layer 240 can berecessed by: chemical mechanical polishing the isolation layer 240 toform a flat surface (e.g., a flat surface in which isolation layer 240and the top of fin structures 210 are co-planar); etching isolationlayer 240 and doping layer 230 to achieve the desired thickness incontact with fin structure(s) 210, for example using a dry and/or wetetching process that removes the material of isolation layer 240 and thematerial of doping layer 230, but not the material of fin structure(s)210.

In such a case, upper surfaces of isolation layer 240 and doping layer230 can be co-planar, and specific thicknesses of doping layer 230 incontact with fin structure(s) 210 can be achieved. As illustrated, afterrecessing, doping layer 230 is provided with a first thickness T₁ infirst region 201 and a second thickness T₂ in second region 201.

In one embodiment, numerous different regions of structure 200 can bedefined, with doping layer 230 provided with a different thickness ineach such region. In addition, dozens of different regions could bedefined, with a different thickness of doping layer 230 in each suchregion.

FIG. 2H depicts structure 200 after annealing doping layer 230 todiffuse dopants 231 into fin structure(s) 210 to form doped middleportion(s) 212 thereof, in accordance with one or more aspects of thepresent invention. In one embodiment, isolation layer 220 inhibitsdiffusion of dopants 231 from doping layer 230 into lower portion(s) 213of the at least one fin structure. In another embodiment, because dopinglayer 230 is not in contact with upper portions of the fin structures,no dopants will diffuse into the upper portions.

In one example, after annealing doping layer 230, doped middleportion(s) 212 of fin structure(s) 210 can have a dopant concentrationof approximately 10¹⁸ to 10²⁰ atoms per cm³. In another example, dopants231 laterally diffuse from doping layer 230 into middle portion(s) 212of fin structure(s) 210. In a further example, the doping layer can bein contact with both sides of the fin structure, thereby facilitatinguniform doping of the middle portions of the fin structures.

In one embodiment, the annealing can be thermal furnace annealing, rapidthermal annealing, or laser annealing. In one specific example, thermalfurnace annealing can be used at a temperature of 600-1,000° C. for 5-30minutes.

In the embodiment of FIG. 2H, first doped middle portion(s) 212 of finstructure(s) 210 in first region 201 can have a first thickness T₁, andsecond doped middle portion(s) 212 of fin structure(s) 210 in secondregion 201 can have a second thickness T₂.

FIG. 2I is a plan view of structure 200, in accordance with one or moreaspects of the present invention. As indicated in FIG. 2I, the crosssectional elevational view of FIG. 2H is taken along line 2H-2H of FIG.2I. In the plan view of FIG. 2I, structure 200 is or includes anintegrated circuit having, for example, first transistors in firstregion 201 and second transistors in second region 202.

In one embodiment, each transistor has a source region 215 separatedfrom a drain region 216 by a channel region which is or includes anupper portion 211 of a fin structure 210 (see FIG. 2H). In addition, achannel region of the transistor can include multiple fin structures210, so that the transistor can have a greater amount of current flowduring its on-state. Further, source regions 215 and drain regions 216can be fabricated by forming cavities in the fin structures 210 and thenproviding a semiconductor material within the cavities. For example,source regions 215 and drain regions 216 can be epitaxially formed within the cavities, such as by growing a semiconductor material (e.g.,silicon or silicon germanium) therein.

In another embodiment, the doped middle portion of fin structure(s) 210reduces leakage current between the channel region of the transistor andthe lower portion of fin structure(s) 210, including, for example,substrate 205. For example, leakage current can be reduced duringoperation of the transistor, such as when the transistor is in theon-state, thereby reducing power consumption and/or heat generation.

In a further embodiment, a first transistor in first region 210 caninclude first fin structure(s) 210 and a second transistor in secondregion 210 can include second fin structure(s) 210. In such a case,first thickness T₁ of first doped middle portion(s) 212 facilitates thefirst transistor having a first threshold voltage characteristic and thesecond thickness T₂ of second doped middle portion(s) facilitates thesecond transistor having a second threshold voltage characteristic,where the first threshold voltage characteristic and the secondthreshold voltage characteristic are different threshold voltagecharacteristics. In a similar manner, numerous regions can be formedwith numerous threshold voltages. For example, three different p-typeregions can be defined with three different threshold voltages, andthree different n-type regions can be defined with three same or similarthreshold voltages, such as a regular threshold voltage (RVT) greaterthan a low threshold voltage (LVT) greater than a super-low thresholdvoltage (SLVT). In such a case, CMOS circuits can be formed usingmatched n-type and p-type transistors with the same or similar thresholdvoltages.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprise” (andany form of comprise, such as “comprises” and “comprising”), “have” (andany form of have, such as “has” and “having”), “include” (and any formof include, such as “includes” and “including”), and “contain” (and anyform of contain, such as “contains” and “containing”) are open-endedlinking verbs. As a result, a method or device that “comprises,” “has,”“includes,” or “contains” one or more steps or elements possesses thoseone or more steps or elements, but is not limited to possessing onlythose one or more steps or elements. Likewise, a step of a method or anelement of a device that “comprises,” “has,” “includes,” or “contains”one or more features possesses those one or more features, but is notlimited to possessing only those one or more features. Furthermore, adevice or structure that is configured in a certain way is configured inat least that way, but may also be configured in ways that are notlisted.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below, if any, areintended to include any structure, material, or act for performing thefunction in combination with other claimed elements as specificallyclaimed. The description of the present invention has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the invention in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The embodiment was chosen and described in order to best explain theprinciples of one or more aspects of the invention and the practicalapplication, and to enable others of ordinary skill in the art tounderstand one or more aspects of the invention for various embodimentswith various modifications as are suited to the particular usecontemplated.

1-20. (canceled)
 21. A method comprising: fabricating at least one finstructure, the at least one fin structure comprising a doped middleportion separating an upper undoped portion from a lower undopedportion, and the fabricating comprising: providing an isolation layer incontact with the lower portion of the at least one fin structure;forming a doping layer above the isolation layer and in contact with theat least one fin structure; and diffusing dopants from the doping layerinto the at least one fin structure to form the doped middle portionthereof and inhibiting diffusion of dopants into the upper undopedportion and lower doped portion
 22. The method of claim 21, wherein themethod comprises: fabricating a transistor having a channel region, thechannel region comprising the upper portion of the at least one finstructure, wherein the doped middle portion of the at least one finstructure reduces leakage current between the source region and thedrain region of the transistor.
 23. The method of claim 21, wherein theat least one fin structure comprises at least one first fin structureand at least one second fin structure, and the fabricating comprises:forming the doping layer with a first thickness in contact with the atleast one first fin structure and a second thickness in contact with theat least one second fin structure; and annealing the doping layer toform a first doped middle portion of the at least one first finstructure with the first thickness and a second doped middle portion ofthe at least one second fin structure with the second thickness, whereinthe first thickness and the second thickness are different thicknesses.24. The method of claim 23, wherein the method comprises: fabricating anintegrated circuit comprising a first transistor and a secondtransistor, the first transistor comprising the at least one first finstructure and the second transistor comprising the at least one secondfin structure, and the first thickness of the first doped middle portionthe first transistor having a first threshold voltage characteristic andthe second thickness of the second doped middle portion facilitates thesecond transistor having a second threshold voltage characteristic,wherein the first threshold voltage characteristic and the secondthreshold voltage characteristic are different threshold voltagecharacteristics.
 25. The method of claim 21, wherein the at least onefin structure comprises at least one first fin structure and at leastone second fin structure, and the fabricating comprises: forming thedoping layer with first dopants in contact with the at least one firstfin structure and second dopants in contact with the at least one secondfin structure, wherein the first dopants and second dopants aredifferent dopants; and annealing the doping layer to form a first dopedmiddle portion of the at least one first fin structure having the firstdopants and a second doped middle portion of the at least one second finstructure having the second dopants.
 26. The method of claim 25, whereinthe first dopants comprise n-type dopants and the second dopantscomprise p-type dopants, and the method comprises: fabricating anintegrated circuit comprising a p-type transistor and an n-typetransistor, the p-type transistor comprising the at least one first finstructure and the n-type transistor comprising the at least one secondfin structure.
 27. The method of claim 21, wherein the at least one finstructure comprises at least one first fin structure and at least onesecond fin structure, and the fabricating comprises: forming the dopinglayer with a first initial dopant concentration in contact with the atleast one first fin structure and a second initial dopant concentrationin contact with the at least one second fin structure, wherein the firstinitial dopant concentration and the second initial dopant concentrationare different concentrations; and annealing the doping layer to form afirst middle portion of the at least one first fin structure with afirst final dopant concentration and a second middle portion of the atleast one second fin structure with a second final dopant concentration,wherein the first final dopant concentration and the second final dopantconcentration are different dopant concentrations.
 28. The method ofclaim 27, wherein the method comprises: fabricating an integratedcircuit comprising a first transistor and a second transistor, the firsttransistor comprising the at least one first fin structure and thesecond transistor comprising the at least one second fin structure, andthe first concentration of the dopants facilitates the first transistorhaving a first threshold voltage characteristic and the secondconcentration of the dopants facilitates the second transistor having asecond threshold voltage characteristic, wherein the first thresholdvoltage characteristic and the second threshold voltage characteristicare different threshold voltage characteristics.
 29. The method of claim21, wherein the fabricating comprises: providing a substrate underlyingthe at least one fin structure; and implanting other dopants into thesubstrate to form a substrate well region thereof, wherein the otherdopants and the dopants of the doping layer are different dopants. 30.The method of claim 21, further comprising: forming a conformal gatestructure over the isolation material and in contact with the at leastone fin structure, wherein the isolation material facilitates aligningthe conformal gate structure in contact with the upper portion of the atleast one fin structure but not in contact with the doped middle portionthereof.
 31. The method of claim 21, further comprising annealing thedoping layer to facilitate diffusing dopants from the doping layer intothe middle portion of the at least one fin structure.
 32. The method ofclaim 21, wherein forming the doping layer comprises epitaxially forminga material over the at least one fin structure to form the doping layer.33. The method of claim 21, wherein forming the doping layer comprisesproviding a material, and concurrently therewith doping the materialwith the dopants, to form the doping layer.
 34. A semiconductorstructure comprising: a FinFET having at least one fin structure whereina middle portion of the fin structure is doped, and wherein an upperportion of the fin structure above the middle portion and a lowerportion of the fin structure below the middle portion are both undoped.35. The structure of claim 34 wherein the structure comprises a channelregion within the upper portion of the at least one fin structure. 36.The structure of claim 35 wherein middle portion of the at least one finstructure reduces leakage current between a source region and drainregion of a transistor.
 37. The structure of claim 36 wherein thestructure comprises: an integrated circuit comprising a first transistorand a second transistor, the first transistor comprising the at leastone first fin structure and the second transistor comprising the atleast one second fin structure, and the first thickness of the firstdoped middle portion the first transistor having a first thresholdvoltage characteristic and the second thickness of the second dopedmiddle portion facilitates the second transistor having a secondthreshold voltage characteristic, wherein the first threshold voltagecharacteristic and the second threshold voltage characteristic aredifferent threshold voltage characteristics.
 38. The structure of claim36 further comprising: a substrate underlying the at least one finstructure; and implanting other dopants into the substrate to form asubstrate well region thereof, wherein the other dopants and the dopantsof the doping layer are different dopants.
 39. The structure of claim 36wherein dopants within the middle portion comprise at least one ofboron, phosphorous or arsenic.
 40. The structure of claim 34 wherein themiddle portion of the fin structure is oxidized.